COMPUTER ARCHITECTURE UNIT V
UNIT V- I/O ORGANIZATION
1. Why IO devices cannot be directly be connected to the system bus?
Ans: The IO devices cannot be directly connected to the system bus because
- The data transfer rate of IO devices is slower that of CPU.
- The IO devices in computer system has different data formats and work lengths that of CPU.
So it is necessary to use a module between system bus and IO device called IO module or IO system
2. What are the major functions of IO system?
Ans: i. Interface to the CPU and memory through the system bus.
ii. Interface to one or more IO devices by tailored data link.
3. What is an I/O Interface?
Ans: Input-output interface provides a method for transferring binary information between internal storage, such as memory and CPU registers, and external I/O devices
4. Write the factors considered in designing an I/O subsystem?
- Data Location: Device selection, address of data with in device( track, sector etc)
- Data transfer: Amount, rate to or from device.
- Synchronization: Output only when device is ready, input only when data is available.
- I/O operation: refers to a data transfer between an I/O device and Memory or between an I/O device and CPU.
5. Explain Direct Memory Access.
Ans: A modest increase in hardware enables an IO device to transfer a block of information to or from memory without CPU intervention. This task requires the IO device to generate memory addresses and transfer data through the bus using interface controllers.
6. Define DMA controller.
Ans: The I/O device interface control circuit that is used for direct memory access is known as DMA controller.
7. What is polling?
Ans: Polling is a scheme or an algorithm to identify the devices interrupting the processor. Polling is employed when multiple devices interrupt the processor through one interrupt pin of the processor.
8. What is the need of interrupt controller?
Ans: The interrupt controller is employed to expand the interrupt inputs. It can handle the interrupt requests from various devices and allow one by one to the processor.
9. What is a Priority Interrupt?
Ans: A priority interrupt is an interrupt that establishes a priority over the various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously.
10. Define bus.
Ans: When a word of data is transferred between units, all the bits are transferred in parallel over a set of lines called bus. In addition to the lines that carry the data, the bus must have lines for address and control purposes.
11. Define synchronous bus.
Ans: Synchronous buses are the ones in which each item is transferred during a time slot(clock cycle) known to both the source and destination units. Synchronization can be achieved by connecting both units to a common clock source.
12. Define asynchronous bus.
Ans: Asynchronous buses are the ones in which each item being transferred is accompanied by a control signal that indicates its presence to the destination unit. The destination can respond with another control signal to acknowledge receipt of the items.
13. What do you mean by memory mapped I/O?
Ans: In Memory mapped I/O, there are no specific input or output instructions. The CPU can manipulate I/O data residing in interface registers with the same instructions that are used to manipulate memory words i.e. the same set of instructions are used for reading and writing memory can be used to input and output.
14. What is program-controlled I/O?
Ans: In program controlled I/O the processor repeatedly checks a status flags to achieve the required synchronization between the processor and an input and output device.
15. Define interrupt.
Ans: An interrupt is any exceptional event that causes a CPUU to temporarily transfer control from its current program to another program , an interrupt handler that services the event in question.
16. Define exception.
Ans: The term exception is used to refer to any event that causes an interruption
17. What are the different methods used for handling the situation when multiple interrupts occurs?
Ans: 1) Vectores interrupts
2) Interrupt nesting
3) Simultaneous Requests.
18. What is a privileged instruction?
Ans: To protect the operating system of a computer from being corrupted by user programs, certain instructions can be executed only while the processor is in the supervisor mode. These are called privileged instruction.
19. What is bus arbitration?
Ans: it is process by which the next device to become the bus master is selected and bus mastership is transferred to it. There are two ways for doing this:
1. Centralized arbitration
2. Distributed arbitration.
20. What is port? What are the types of port available?
Ans: An I/O interface consists of circuitry required to connect an I/O device to computer bus. One side consists of a data path with its associated controls to transfer data between the interface and I/O device. This is called port. It is classified into:
1) Parallel port
2) Serial port.
21. What is a parallel port?
Ans: A parallel port transfers data in the form a number of bits, typically 8 to 16, simultaneously to or from the device.
22. What is a serial port?
Ans: A serial port transfers and receives data one bit at a time.
23. What is PCI bus?
Ans: The Peripheral component interconnect(PCI) bus is a standard that supports the functions found on a processor bus but in a standardized format that is independent of any particular processor.
24. What is SCSI?
Ans: It is the acronym for small computer system interface. It refers to a standard bus defined ANSI. Devices such as disks are connected to a computer via 50-wire cable, which can be upto 25 meters in length and can transfer data at rate up to 55 megabytes/s.
25. Define USB.
Ans: The Universal Serial Bus(USB) is an industry standard developed to provide two speed of operation called low-speed and full-speed. They provide simple, low cost and easy to use interconnection system.
16 MARKS QUESTIONS WITH HINTS:
1. What are the functional units of a computer? Explain briefly.
Hints: The different functional units are:
1) Input Unit.
2) Output Unit.
3) Memory Unit.
4) Arithmetic & logic Unit.
5) Control Unit.
Refer Page no. 3-7
2. Explain the basic operational concepts of a computer.
Hints: Explain about the MAR, MDR, and the connection between the processor and the memory with a neat diagram.
Refer page no. 7-9.
3. Describe the different classes of instruction format with example and different
Hints: The different instruction formats are :
1) Three address instruction
2) Two address instruction
3) Zero address instruction
Refer page no. 38-42
The different addressing modes are:
- Immediate addressing mode
- Register addressing mode
- Direct or absolute addressing mode
- Indirect addressing mode
- Indexed addressing mode
- Relative addressing mode
Refer Page no. 48-58.
4. Explain the basic input operations with suitable examples.
Hints: Expalin about program-controlled I/O and memory mapped I/O. Draw the diagram of bus connection for processor , keyboard and display.
Refer Page no. 64-68
5. Write short notes on
i) Software performance
Hints: Refer page no. 10-12.
ii) Memory locations and addresses
Hints: Explain about byte addressability, big endian and little endian assignments, word alignment. Refer page no. 33-36.
6. Describe the multiplication speed up technique with an example.
Hints: There are two techniques to speed up the multiplication process:
1) The first technique guarantees that the maximum number of summands that must be added is n/2 for n-bit operands ie bit pair recoding .
2) The second technique reduces the time needed to add the summands i.e Carry save addition
Refer page no. 383-390
7. Explain the floating point Addition – subtraction unit with neat diagram.
Hints: In some cases, the binary point is variable and is automatically adjusted as computation proceeds. In such case, the binary point is said to float and the numbers are called floating point numbers.
|S E¢ M|
Sign of the 8-bit signed 23- bit Mantissa fraction
Number exponent in excess-127
0 – Positive representations
1 – Negative
value represented= ± 1. M´ 2E¢-127
1) Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents.
2) Set the exponent of the result equal to the larger exponent.
3) Perform addition/subtraction on the mantissa and determine the sign of the result
4) Normalize the resulting value, if necessary.
Refer page no. 393-402. Draw the diagram.
8. Explain the organization of a sequential binary multiplier with example.
Hints: Explain about the sequential circuit binary multiplier with registers. Write the procedure.
Draw the diagram. Refer page no. 376-379.
9. Explain the Booth algorithm. Multiply 11´-9 using Booth algorithm
Hints: Explain about the Booth algorithm.The advantages are:
1) It handles both positive and negative multiplier uniformly.
2) It achieves efficiency in the number of additions required when the multiplier has a few large blocks of 1’s.
3) The speed gained by skipping 1’s depends on the data
10. Explain the Integer division techniques with suitable example.
Hints: The algorithm for restoring division:
Do the following for n times:
1) Shift A and Q left one binary position.
2) Subtract M and A and place the answer back in A.
3) If the sign of A is 1, set q0 to 0 and add M back to A.
Where A- Accumulator, M- Divisor, Q- Dividend
Give an example.
The algorithm for non restoring division:
Do the following for n times:
Step 1: Do the following for n times:
1) If the sign of A is 0 , shift A and Q left one bit position and subtract M from A; otherwise , shift A and Q left and add M to A.
2) Now, if the sign of A is 0,set q0 to 1;otherwise , set q0 to0.
Step 2: if the sign of A is 1, add M to A.
Give an example.
Refer page no. 390-393.
11. Explain the multiple bus organization structure with neat diagram.
Hints: The multiple bus organization is using more buses instead of one bus to reduce the number of steps needed and to provide multiple paths that enable several transfers to take place in parallel.
Refer page no. 423-425.
12. Describe the Hardwired control method for generating the control signals
Hints: Hard-wired control can be defined as sequential logic circuit that generates specific sequences of control signal in response to externally supplied instruction
Refer page no. 425- 429
13.Describe the micro programmed control unit in detail.
Hints: A micro programmed control unit is built around a storage unit is called a control store where all the control signals are stored in a program like format. The control store stores a set of micro programs designed to implement the behavior of the given instruction set.
Refer page no. 429-445
14. Give the organization of the internal data path of a processor that supports a 4-stage pipeline for instructions and uses a 3- bus structure and discuss the same.
Hints: The speed of execution of programs can be improved by arranging the hardware so that more than one operation can be performed at the same time.
Explain about the 4- stage pipeline.
Refer page no. 4556-459
For 3- bus structure refer page no. 479-481.
15. What is pipelining? What are the various hazards encountered in pipelining?
Explain in detail.
Hints: The major characteristics of a pipeline are:
a) Pipelining cannot be implemented on a single task, as it works by splitting multiple tasks into a number of subtasks and operating on them simultaneously.
b) The speedup or efficiency achieved by suing a pipeline depends on the number of pipe stages and the number of available tasks that can be subdivided.
c) If the task that can be subdivided has uneven length of execution times, then the speedup of the pipeline is reduced.
d) Though the pipeline architecture does not reduce the time of execution of a single task, it reduces the overall time taken for the entire job to get completed.
The various pipeline hazards are:
1. Data hazard
2. Structural Hazard
3. Control Hazard.
Refer page no. 459-476.
16. Describe the three mapping techniques used in cache memories with suitable
Hints: The cache memory is a fast memory that is inserted between the larger slower main memory and the processor. It holds the currently active segments of a program and their data.
i) Associative mapping.
ii) Direct mapping.
iii) Set-associative mapping
Refer page no. 314-325
17. Explain with neat diagram the internal organization of bit cells in a memory
Hints: Memory cells are usually organized in the form of an array, in which each cell is capable of storing one bit of information. Each row consists a memory word, and all cells of a row are connected to a common line referred to as word line, which is driven by he address decoder on the chip.
Refer Page no. 295-297.
18. Discuss the virtual memory management technique in detail
|W: Write inst.|
|E: Execute inst|
& fetch inst
|F: Fetch instruction|
Hints: The data is to be stored in physical memory locations that have addresses different from those specified by the program. The memory control circuitry translates the address specified by the program into an address that can be used to access the physical memory.
Refer page no. 337-343
19. Explain the various secondary storage devices in detail.
Hints: The various secondary storage devices are:
1. Magnetic hard disks
2. Optical disks
3. Magnetic tape systems Refer page no. 344-359
20. What is memory interleaving? Explain with neat diagram.
Hints: The main memory of a computer is structure as a collection of physically separate modules each with its own address buffer register and data buffer register, memory access operations may proceed in more than one module at the same time. Thus the aggregate rate of transmission of words to and from the main memory system can be increased.
Refer page no. 330-331
21. Describe the data transfer method using DMA.
Hints: A modest increase in hardware enables an IO device to transfer a block of information to or from memory without CPU intervention. This task requires the IO device to generate memory addresses and transfer data through the bus using interface controllers.
Refer page no. 234-240.
22. Explain about the interrupts in detail
Hints: An interrupt is any exceptional event that causes a CPUU to temporarily transfer control from its current program to another program , an interrupt handler that services the event in question.
Refer page no. 208-221.
23. Explain the different types of buses with neat diagram.
Hints: When a word of data is transferred between units, all the bits are transferred in parallel over a set of lines called bus. In addition to the lines that carry the data, the bus must have lines for address and control purposes.The different types of buses are:
1. Synchronous Buses:
Synchronous buses are the ones in which each item is transferred during a time slot(clock cycle) known to both the source and destination units. Synchronization can be achieved by connecting both units to a common clock source.
2. Asynchronous buses
Asynchronous buses are the ones in which each item being transferred is accompanied by a control signal that indicates its presence to the destination unit. The destination can respond with another control signal to acknowledge receipt of the items.
Refer page no. 241-247
24. Explain the various interface circuits.
Hints: An I/O interface consists of circuitry required to connect an I/O device to computer bus. One side consists of a data path with its associated controls to transfer data between the interface and I/O device. This is called port. It is classified into:
1) Parallel port
2) Serial port.
Refer page no. 248-259.
25. Explain in details the various standard I/O interfaces.
Hints: The various standard I/O interfaces are:
1. The Peripheral component interconnect(PCI) bus is a standard that supports the functions found on a processor bus but in a standardized format that is independent of any particular processor
2. It is the acronym for small computer system interface. It refers to a standard bus defined ANSI. Devices such as disks are connected to a computer via 50-wire cable, which can be upto 25 meters in length and can transfer data at rate up to 55 megabytes/s.
3. The Universal Serial Bus(USB) is an industry standard developed to provide two speed of operation called low-speed and full-speed. They provide simple, low cost and easy to use interconnection system.
Refer Page no. 259-281.